A low distortion, high speed switched capacitor sample and hold circuit has been designed. A novel bootstrapped switch is used to degrade the nonlinearity and the method to decrease the settling time of the amplifier is proposed. 设计了一种低失真、高速的开关电容采样保持电路,采用了新型的bootstrapped开关来降低由于开关引入的非线性,并提出了减小放大器的建立时间以减小运算放大器引入的非线性的方法。